DIGITAL ELECTRONICS (ECT-033) UTU

COURSE OBJECTIVES: The objectives of the course are to:

1. Understand the basics of digital electronics.
2. Understand the basics of Logic family.
3. Apply the knowledge of digital electronics to construct various digital circuits.
4. Analyze the characteristics and explain the outputs of digital circuits.
5. Evaluate and asses the application of the digital circuits.
6. Understand the design flow of VLSI Circuits

COURSEOUTCOMES: After completion of the course student will be able to:

1. Understand the Boolean algebra and minimization of digital functions.
2. Design and implement various combinational circuits.
3. Design and implement various sequential circuits.
4. Understand the digital logic families, semiconductor memories.
5. Design the digital circuits using VHDL

Course Content :-

UNIT 1: MINIMIZATION OF LOGIC FUNCTIONS:
Review of logic gate and Boolean algebra, DeMorgan’s Theorem, SOP & POS forms, canonical forms, don’t care conditions, K-maps up to 6 variables, Quine-McClusky’s algorithm, X-OR & X-NOR simplification of K-maps, binary codes, code conversion.

UNIT 2: COMBINATIONAL CIRCUITS:
Combinational circuit design, half and full adders, subtractors, serial and parallel adders, code converters, comparators, decoders, encoders, multiplexers, de-multiplexer, parity checker, driver &multiplexed display, BCD adder, Barrel shifter and ALU.

UNIT 3: SEQUENTIAL CIRCUITS:
Building blocks like S-R, JK and master-slave JK FF, edge triggered FF, ripple and synchronous counters, shift registers, finite state machines, design of synchronous FSM, algorithmic state machines charts, designing synchronous circuits like pulse train generator, pseudo random binary sequence generator, clock generation

UNIT 4: LOGIC FAMILIES & SEMICONDUCTOR MEMORIES:

TTL NAND gate, specifications, noise margin, propagation delay, fan-in, fan-out, tri-state TTL, ECL, CMOS families and their interfacing, memory elements, concept of programmable logic devices like FPGA, logic implementation using programmable devices.

UNIT 5: VLSI DESIGN FLOW: Design entry:
schematic, FSM & HDL, different modelling styles in VHDL, data types and objects, dataflow, behavioral and structural modelling, synthesis and simulation VHDL constructs and codes for combinational and sequential circuits.